This invention relates to a Schottky FET device and a process for manufacturing the same, and in particular, to achieving an easy and effective increase in the mutual conductance of a GaAs FET.
GaAs FETs (field effect transistor), an example of which is the Schottky (junction) FET, are well-known as devices for microwave low-power signals and IC devices for high-speed, low-power-consumption applications.
FIG. 1 shows a simplified prior art GaAs-FET structure, which has a straight bar type gate electrode 1. A source electrode 2 and drain electrode 3, which have straight shapes similar to that of the gate electrode 1, are provided symmetrically separated by an equal distance from this gate electrode 1, which is in the center. FIG. 1 also shows a GaAs semiconductor substrate 4, a channel 5 formed of an N-type low-concentration impurity layer, which is formed on the semiconductor substrate 4, and source and drain regions 6 and 7 formed of N-type high-concentration impurity layers.
This kind of structure has the disadvantage of not being able to produce high performance devices for the following reasons. In the prior art GaAs FET manufacturing process, the source and drain electrodes are positioned symmetrically in relation to the gate electrode so that self-alignment techniques may be used. In this kind of structure, however, when the distance between the gate and source electrodes is decreased in order to increase the mutual conductance, the distance between the gate and drain electrodes is also decreased so the drain withstand voltage decreases. This means that there is a decrease in the distance margin, the result of which is a drastic degradation in manufacturing yield. Accordingly, in the past it has been impossible to improve the mutual conductance of the devices and still obtain a good manufacturing yield.
The reason the gate electrode of the prior art GaAs FET of FIG. 1 is made straight is in order to make it possible to use a lift-off manufacturing technique. This kind of straight gate electrode is not suitable for making high performance FETs. The lift-off technique is capable of producing narrow wiring lines but when the wiring is curved, it is extremely difficult to keep the width constant. Consequently, when such a lift-off technique is used the wiring must be designed without any curves, and accordingly, the gate electrode of the prior art GaAs FET also is formed straight using the lift-off technique.
However, in general in order to produce devices having high mutual conductance, it is necessary to increase the gate width W, so if the gate electrode is straight as in the prior art and one tries to achieve high mutual conductance in the devices, not only does the width of the gate increase, but that of the drain and source as well, which results in devices of large area. Accordingly, it is impossible to achieve compact, high performance GaAs FETs with a structure such as that shown in FIG. 1, which has a straight gate electrode.
For these reasons, it is impossible with the prior art device structure to produce a GaAs FET of high mutual conductance without reducing the drain withstand voltage and reducing the manufacturing yield, and it is impossible to produce compact, area-efficient, high performance devices.
In order to solve these problems, the following methods have been proposed: (1) the distance between the source and gate electrodes is made short while that between the drain and gate electrodes is made long to thereby increase the mutual conductance and the drain withstand voltage, (2) by encircling the source or drain with a loop-shaped gate electrode, the gate width is increased, and high mutual conductance is obtained along with devices having high area efficiency. The first method, however, has the drawback that self alignment techniques cannot be used and it is impossible to sufficiently decrease the distance between the gate and source for greater patterning accuracy. No detailed, practical proposal has been made for the second manufacturing method.